The present invention relates to testing of integrated circuit devices and, in particular, to testing packet-based semiconductor memories and the devices themselves.
As the complexity of semiconductor integrated circuits continues to increase, difficulties begin to arise in the use of generalized test equipment to ensure the desired operability of each device. The increasing complexity of these devices is driven largely by the need to increase speed and bandwidth and, as such, the architecture of these devices changes to achieve this result. These changes in device architecture, in many cases, make the utilization of existing test equipment difficult, if not impossible. Purchasing new test equipment is often economically undesirable, particularly if only a segment of a production line utilizes these device architectures.
The generalized test equipment used to test semiconductor integrated circuits may vary between manufacturer and intended use, but in general, the test equipment is used to monitor processes, test board and box level assemblies, and may be used to test the functionality of an integrated circuit.
One type of test equipment that is of particular interest in the case of manufacturing memory devices is referred to as a xe2x80x9cmemory tester.xe2x80x9d Hereinafter, the terms xe2x80x9cmemory testerxe2x80x9d and xe2x80x9ctesterxe2x80x9d will be used interchangeably. Memory testers allow for the functional testing of integrated memory circuits to identify defects at the time of test. Identification of a defective device gives the manufacturer the options of reworking, repairing, or possibly scrapping the device. Because of the cost added at each step of the manufacturing process, the earlier a defect can be discovered, the more cost efficient the manufacturing process will be.
Functionally testing integrated memory circuits typically involves the development of a logical model of the device to be tested. The model defines input pins for the application of stimuli to the device under test (DUT) and output pins for observation of the response from the DUT. Logical models are typically developed with the requirements of the intended tester in mind. With an accurate model, a measured response from a DUT can be compared against the anticipated model response, and if it does not match, then a faulty device has been detected.
In a typical tester, an algorithmic pattern generator (APG) is provided as a resource for stimuli of the input pins of a DUT. The APG typically provides a first X address generator and a second Y address generator. To illustrate the operation of an APG, imagine writing zeros into every address of a DUT. In this case, the data generator would generate a continuous xe2x80x9c0.xe2x80x9d The X address generator would run from xe2x80x9c0xe2x80x9d to a predefined end address, whereas the Y address generator would maintain its initial value. Once the X address generator reaches its end address, it would be reset to xe2x80x9c0,xe2x80x9d the Y address generator would be increased by one, and the X address generator would again run from xe2x80x9c0xe2x80x9d to its end address. This process would continue until all cells of the memory under test contained a xe2x80x9c0.xe2x80x9d
The controller of such an APG typically includes a programmable vector memory for storing test patterns. Vector memory is typically limited in size. If a sufficiently large number of test patterns are necessary to test a given device, it may require loading more than one set of test patterns in vector memory to complete the test. Thus, it is advantageous to use an APG where possible to preserve available vector memory and allow for more efficient operation.
A packet-based semiconductor memory operates on more than one word of information in a given cycle. The packet information could be data, address, command or any other type of data which the device is capable of receiving or outputting. The number of words in a given packet cycle is determined by the particular device architecture. The term xe2x80x9cdata packetsxe2x80x9d and xe2x80x9cpacketsxe2x80x9d are used interchangeably herein to include data, address and command information.
Because many tester APGs have only X and Y address generators, it is difficult to generate more than two bits of APG data as input stimuli to a DUT. The same problem would arise for an APG with N address generators if one was attempting to generate more than N bits of APG data. Herein lies the problem with testing integrated memory circuits which require packet-based information. With packet-based devices, there may be a need for more than two bits of APG data per input pin as stimuli. This may require the use of vector memory to supply the additional information bits.
To illustrate the problem, consider, for example, the draft specification for a 4 Megabitxc3x9718 I/O Synchronous-Link Dynamic Random Access Memory (SLDRAM). The draft specification for this packet-based semiconductor memory is titled Draft/Advance, SLDRAM Inc., SLD4M18DR400, 4 MEGxc3x9718 SLDRAM, Rev. Feb. 12, 1998. FIG. 1 is a table reproducing the information in a Read, Write or Row Operation Request Packet, as defined in the above-referenced draft specification, page 7, which comprises four 10-bit words, WORD 0, WORD 1, WORD 2, and WORD 3. As depicted, the first row of data under the column heading represents prior data in a packet stream, which are not of concern, hence the xe2x80x9cdon""t carexe2x80x9d or xe2x80x9cxxe2x80x9d value placed within each bit location. Each column of data represents an input pin on the SLDRAM device, including the Flag bit. The Command Address bits, CA0-CA9, define the 10-bit command words. The beginning of a packet is indicated by the Flag bit being in a logical true. The Flag bit logical true also indicates that the first word in a packet, WORD 0, is present on the CA0-CA9 bits.
The data within each of the four command words, WORD 0-3, are latched with timing signals not shown in FIG. 1. WORD 0 contains the nine identification bits, ID0-ID8, used to identify a particular SLDRAM in an array of such memory devices, as well as CMD5, which is one of six command code bits. WORD 1 contains CMD0-4, BNK0-2, and ROW8-9. The command bits CMD0-5 are used to instruct the SLDRAM to perform a particular memory operation. For example, where all six of the CMD0-5 bits are zero, the command is: Page Access, Burst of 4, Read Access, Leave Row Open, Drive DCLK0. The bank address bits BNK0-2 are used to select one of eight memory banks, where each memory bank is 1024 rowsxc3x97128 columnsxc3x9772 bits in size. WORD 2 contains eight of the row address bits, ROW0-7, and two unused bits. WORD 3 contains seven column address bits, COL0-6, and three unused bits.
The address bits, bank, row and column are particularly suitable for algorithmic pattern generation because it is frequently the case that one wants to sequence through the addresses when performing a read or write operation. In contrast, the command code bits CMD0-5 are accessed in a more or less random order, so vector memory is more appropriate and convenient as a source of test patterns. In FIG. 1, this test pattern source preference has been indicated by the abbreviations xe2x80x9cvmxe2x80x9d for vector memory and xe2x80x9capgxe2x80x9d for algorithmic pattern generator.
Ideally, the bank, row and column addresses would each be assigned one of the address generators in the APG. However, as noted above, conventional APGs typically have only two address generators, X and Y. To illustrate the problem, refer to FIG. 1, column CA3, which represents command address pin 3. For pin CA3, the tester must provide three pieces of algorithmic data, BNK1, ROW1, and COL3, in addition to ID2, which is sourced from vector memory. Furthermore, WORDs 1-3 contain combinations of data from vector memory and an APG.
In most cases, it is possible to create a description of a combination of required vectors and APG bits to accommodate each of the cycles described in a typical packet. This approach, however, requires much additional work to format pins appropriately and may consume additional tester resources.
The cost of testing is a significant portion of integrated circuit manufacturing costs. Digital integrated circuit testers (specifically memory testers) can be costly and require significant calibration and maintenance expenses over time. The useful life of such a tester is limited by its designxe2x80x94the number of pins, pattern depth, and signal generating and comparison speeds. These and other factors limit the number of applications the tester can be used for, due to changes in integrated circuit architecture, increasing signal speeds, increasing disparity of signal speeds, and the increasing number of functions designed into a single integrated circuit package. While it is always an option to purchase state-of-the-art test equipment to accommodate a new generation of IC, the cost is prohibitive unless absolutely necessary.
Because of the increased costs associated with designing test programs to test packet-oriented memory devices and the limited resources of conventional memory testers, there is a need in the art for devices or methods to test packet-based semiconductor memory devices by rearranging the signals within words of a predefined packet to allow simplified and lower cost testing with conventional tester architecture.
To overcome the problem of testing semiconductors with packet-based architectures using conventional memory test equipment, the apparatus and system of the present invention utilizes data realignment circuitry. To avoid confusion, the following terminology will be used throughout this application. The DUT is designed to accept packets in a first or xe2x80x9crealignedxe2x80x9d format. A conventional tester may be employed to generate test data packets in a second format different from the first. This second format is also referred to as xe2x80x9cfacilitatedxe2x80x9d test data. The data realignment circuitry of the present invention realigns test data packets from the second, facilitated format into test data packets in the first format, which the DUT can recognize. The invention reduces the number of required tester resources on a per-pin basis. In other words, the inventive test mode circuitry reformats easily generated or simplified (i.e., facilitated) test data to conform with a given packet definition or specification that would otherwise be difficult to generate directly with conventional test equipment. The invention also provides methods of generating simplified test data from conventional memory test equipment and methods of realigning the simplified test data to the proper packet data specification.
FIG. 2 represents the same packet information as in a conventional Read, Write, or Row Operation Request packet definition for a 4 Mxc3x9718 SLDRAM (four, 10-bit command address words, plus a Flag bit), but in a format that is easier to produce with conventional memory testers in accordance with the invention. Note that there is a one-to-one correspondence between the information in FIG. 1 and FIG. 2. More specifically, WORD 0 contains identification bits, ID0-8. It should be noted that it is a simple task to generate the desired identification bit data from vector memory (if required) in a single word or tick of a packet. WORD 1 contains command bits, CMD0-5, which can also be sourced easily from vector memory. WORD 2 contains the row address bits, ROW0-9, which are ideally generated using a single address generator from an APG. And finally, WORD 3 contains bank address bits, BNK0-2, and column address bits, COL0-6, which are ideally generated by one or two address generators in an APG. Note more importantly, that none of the command address bits, CA0-9, contain more than two pieces of algorithmic data.
This facilitated SLDRAM packet data is then converted back to the original SLDRAM-recognizable packet format with the inventive test mode data realignment circuitry for use by the remaining conventional SLDRAM circuitry per its specification. The inventive test mode realignment circuitry can be implemented in any one of a number of preferred embodiments.
A first embodiment of the present invention incorporates a discrete block of data realignment circuitry on an SLDRAM located between the command and address and Flag pins and the command and address capture or latching circuitry.
A second embodiment of the present invention integrates the data realignment function with the command and address latching function. Still further embodiments move the data realignment function off-chip to, respectively, a test interface and a memory tester. Computer systems may be fabricated using memory chips incorporating the inventive data realignment testing scheme. These embodiments and attendant advantages of the invention will be readily understood by reading the following detailed description in conjunction with the accompanying figures of the drawings.